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S3C2800 32 - bit risc microprocessor data sheet revision 1.0
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s 3c2800 32 - bit risc microprocessor data sheet overview samsung's S3C2800 32 - bit risc micro processor is designed to provide a cost - effective and high - performance micro - controller solution for general applications. the S3C2800 features the following integrated on - chip support to help design a system a low cost: 16kb i/d caches, 2 - ch uart with handshake, 4 - ch dma, memory controller, 3 - ch timer, gpio (general - purpose input/output) ports, rtc (real time clock), 2 - ch iic - bus interface, and a built - in pll for system clock. based on arm920t core, the S3C2800 is developed using 0.18 um cmos standard cells and a memory compiler. its simple, elegant, and fully static low - power design is particularly suitable for both cost - sensitive and power - sensitive applications. the 32 - bit arm920t risc processor core (220mips @200mhz), designed by advanced risc machines, ltd., provides architectural enhancements such as the thumb de - compressor, a 32 - bit hardware multiplier, and an on - chip ice debug support. also, the S3C2800 features the harvard bus architecture for efficient data/instruction transfers. by integrating various common system peripherals, the S3C2800 minimizes the overall system cost and eliminates the need to configure additional components. the integrated on - chip functions are summarized as follows : pci b us interface (32 - bit, up to 66mhz). 1.8v static arm920t cpu core with 16kb i/d (instruction/data) cache. (harvard bus architecture up to 200mhz). external memory controller. (fp/edo/sdram control, chip select logic). 4 - ch general dmas with external request pins. 2 - ch uart with handshake (irda1.0, 16 - byte fifo), modem interface. 2 - ch multi - master iic - bus controller. 3 - ch 16 - bit timer. 16 - bit watchdog timer. 44 general - purpose gpio ports including 8 external interrupt source. power management: normal, slow, and idle modes. rtc with calendar function. on - chip pll clock generator.
S3C2800 microcontrol ler data sheet 2 features architecture little - /big - endian support for external memory. address space: 32mbytes per each bank (total 256mbyte) supports programmable 8/16/32 - bit data bus width for each memory bank fixed bank start address for all (static memory and dynamic memory banks) 8 memory banks ? 4 memory banks for static memory (rom, sram, flash etc) ? 4 memory banks for dynamic memory (fast page, edo, and synchronous dram) fully programmable access cycles for all static memory banks supports external wait signal to extend the bus cycle supports self - refresh mode in dram/sdram. supports asymmetric/symmetric address of dram i/d (instruction/data) cache memory 64 - way set - associative icache (16kb) and dcache (16kb) 8 words per line with one valid bit and 2 dirty bits per line pseudo - random or round - robin replacement algorithm write - through and write - back cache operation. the write buffer can hold 16 words of data and 4 addresses low voltage cache for reduced power consumption clock & power manager the on - chip pll generates the necessary clock for the operatio n of mcu at maximum of 200mhz@1.8v input frequency range: (fin) = 6mhz ? 10mhz. output frequency range: (f clk ) = 20mhz ? 200mhz clock can be selectively provided to each function block by software power down mode: normal , slow , and idle mode ? normal mode: normal operating mode ? slow mode: low frequency clock without pll ? idle mode: clock to cpu is disabled pci bus interfa ce embedded pci host bridge 32 - bit data bus at 66mhz
data sheet S3C2800 m icrocontroller 3 features (c ontinued ) interrupt controller 34 interrupt sources. (3 for timers, 6 for uart, 8 for external interrupts, 4 for dma, 2 for rtc, 2 for iic, 2 for rcsr (remote control signal receiver), and 7 for pci )) software polling interrupt mode selectable level - or edge - triggered external int errupts source programmable irq/fiq for each interrupt request supports fiq (fast interrupt request) for very urgent interrupt request timer 3 - ch 16 - bit timer with dma - based or interrupt - based operation watchdog timer 16 - bit watchdog timer rcsr (remote control signal receiver) 8 - step fifo fifo interrupt is generated on full (8) step overflow rtc (real time clock) full clock feature: sec, min, hour, date, day, week, month, and year 32.768 khz input clock alarm interrupt time tick interrupt gpio (general - p urpose i nput/ o utput) p orts 8 external interrupt ports 44 multiplexed input/output ports. uart 2 - c hannel uart with dma - based or interrupt based operation supports 5 - bit, 6 - bit, 7 - bit, or 8 - bit serial data transmit/receive supports hardware handshaking during transmit/receive operation programmable baud rates (up to 230.4kbps). supports irda 1.0 (up to 115.2kbps) loop back mode for testing program accessible 16 - byte fifo (2x16 byte fifo for transmit/receive data) dma controller 4 - channel general - purpose direct memory access controller without cpu intervention. support memory to memory, memory to i/o and i/o to i/o dma operations of the following 6 types: software, 3 internal function blocks (uart0, uart1, timer), and 2 external requests burst transfer mode to enhance the transfer rate on the fpdram, edodram and sdram iic - bus interface 2 - ch multi - master iic - bus with interrupt - based operation serial, 8 - bit oriented, bi - directional data transfers at up to 100 kbit/s in the standard mode or up to 400 kbit/s in the fast mode operating voltage range core: 1.8 v - 0.1 v/+0.15 v i/o: 3.3 v 0.3 v operating frequency up to 200 mhz. package 208 - pin lqfp
S3C2800 microcontrol ler data sheet 4 block diagram ahb to apb bridge 2ch-iic 2ch-iic 2ch-iic 2ch-iic watch-dog rtc 2ch-iic rmt receive memory controller pci bridge 4ch-gdma arbiter/decode amba bus interface asb asb to ahb bus bridge ahb bus 32-bit bus controller arbiter/decode interrupt controller clock(pll) & power manage 2ch-iic gpio 2ch-uart 3ch-timers ahb to apb bridge apb bus 32-bit write buffer write back pa tag ram data cache data mmu arm9tdmi processor core (integral embeddedice) external coproc interface instruction cache instruction mmu cp15 wbpa[31:0] dpa[31:0] dva[31:0] dd[31:0] id[31:0] ipa[31:0] iva[31:0] iv 2 a[31:0] dv 2 a[31:0] jtag c13 c13 figure 1. S3C2800 block diagram
preliminary data she et S3C2800 microcon troller 5 pin diagram (208 - lqf p) S3C2800x 208-lqfp vss3op vdd3op pci_ad27 pci_ad26 pci_ad25 pci_ad24 120 119 118 117 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 pci_ad17 pci_ad16 vss3op pci_c2/nbe2 pci_nframe pci_nirdy vdd3op pci_ntrdy pci_par pci_nserr pci_nperr pci_nlock pci_nstop pci_ndevsel pci_c1/nbe1 pci_ad15 vss3op pci_ad14 pci_ad13 pci_ad12 pci_ad11 pci_ad6 pci_ad9 pci_c0/nbe0 vdd3op pci_ad8 pci_ad7 pci_ad10 pci_ad19 121 122 123 124 125 126 127 128 pci_c3/nbe3 pci_idsel pci_ad23 pci_ad22 vdd vss pci_ad21 pci_ad20 pci_ad18 105 106 107 108 109 110 111 112 113 114 115 116 53 54 55 56 57 58 60 59 65 64 63 62 61 68 67 66 74 73 72 71 70 69 76 77 78 79 80 75 86 85 84 83 82 81 88 89 90 91 92 87 noe nwe 41 42 43 44 45 46 47 48 49 50 51 52 vdd3op vss3op data29 data30 data31 gpb6/nwait gpb7/clkout gpc0 gpc1 gpc2 gpc3/endian ntrst tck tms tdi tdo irin gpd0/iicsda0 gpd1/iicsclk0 gpd2/iicsda1 gpd6/ncts0 gpd5/txd0 gpd4/rxd0 gpd3/iicsclk1 gpd7/nrts0 nreset_out gpe0/rxd1 gpe1/txd1 gpe2/ncts1 gpe3/nrts1 vdd vss gpe4/nxdreq0 gpe5/nxdack0 gpe6/nxdreq1 gpe7/nxdack1 gpf0/extint0 gpf1/extint1 1 nsdcs2/ndras2/gpa4 nsdcs3/ndras3/gpa5 vdd3op vss3op ndcas0/gpa6 ndcas1/gpa7 ndcas2/nsdcas/gpb0 ndcas3/nsdras/gpb1 sdcke sdclk addr17 data17 nbe0/nwbe0/dqm0/gpb2 nbe1/nwbe1/dqm1/gpb3 nbe2/nwbe2/dqm2/gpb4 nbe3/nwbe3/dqm3/gpb5 data16 addr16 data18 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 addr18 vdd3op vss3op data19 addr19 data20 addr20 vdd vss addr5 data7 addr7 data8 addr8 data9 addr9 vdd vss data10 addr10 data11 addr11 vss3op nsdcs1/ndras1/gpa3 data15 nscs3/gpa2 nscs2/gpa1 nsdcs0/ndras0 nscs0 addr13 addr12 addr14 vdd3op data12 data13 data14 addr15 nscs1/gpa0 addr23 data24 29 30 31 32 33 34 35 36 37 38 39 40 data21 addr21 data22 addr22 data23 addr24 data25 data26 data27 data28 169 170 171 172 173 174 175 176 177 178 179 180 data2 addr2 data3 addr3 vdd3op vss3op data4 addr4 data5 data6 addr6 gpf2/extint2 gpf3/extint3 gpf4/extint4 gpf5/extint5 gpf6/extint6 gpf7/extint7 vdd3op vss3op xtal0 extal0 test nreset 157 158 159 160 161 162 163 164 165 166 167 168 pci_ad5 vss3op pci_ad4 pci_ad3 pci_ad2 pci_ad1 pci_ad0 pci_ninta data0 data1 addr1 pci_nreq1 vss3op pci_nreqx2 pci_nreqx3 pci_ad31 xtal1 extal1 om0 om1 avdd pllcap avss pci_nrst pci_clk pci_ngnt1 pci_ngntx2 pci_ngntx3 98 97 96 95 94 93 100 101 102 103 104 99 addr0 pci_ad29 pci_ad28 pci_ad30 vdd/vss : internal 1.8v power avdd/avss : analog 1.8v power vdd3op/vss3op : i/o 3.3v power figure 2. S3C2800 pin assignment (208 - lqfp)
S3C2800 microcontrol ler data sheet 6 pin assignments table 1. pin assignment description i/o type descriptions vdd1ih, vss3i vdd1ih_pci, vss3i_pci 1.8v power/ground for internal logic vdd1t_abb, vss1t_abb 1.8v power/ground for analog circuitry vdd3op, vss3op vdd3op_pci, vss3op_pci 3.3v power/ground for external interface logic poar50_abb 1.8v analog output (a ca pacitor is connected between the pin and analog ground) phsoscm16 oscillator cell width enable and feedback resistor (6 m ? 40 mhz) phsosck17 oscillator cell width enable and feedback resistor ( ? 100 khz) phis 3.3v interface lvcmos schmitt trigger level input buffers phisu 3.3v interface lvcmos schmitt trigger level input buffers with 100 k w pull - up resistor. phob8 3.3v lvcmos normal output buffers, io = 8 ma phob8sm 3.3v lvcmos normal output buffers with medium slew - rate , io = 8 ma phot8 3.3v lvcmos tri - state output buffers, io = 8 ma phob12 3.3v lvcmos normal output buffers, io = 12 ma phbsud4 3.3v open - drain bi - directional buffers with 100 k w pull - up resistor. io=4ma phbsu50cd4sm 3.3v bi - directional pad, lvcmos schmitt trigger, open - drain, 50 k w pull - up resistor with control, tri - state, io = 4 ma phbsu50ct8sm 3.3v bi - directional pad, lvcmos schmitt trigger, 50 k w pull - up resist or with control, tri - state, io = 8 ma phbsu50ct12sm 3.3v bi - directional pad, lvcmos schmitt trigger, 50 k w pull - up resistor with control, tri - state, io = 12 ma ptipci 3.3v input buffer ptopci 3.3v output buffer with tri - state ptbpci 3.3v bi - directional buffer with input and tri - state output ptbdpci 3.3v bi - directional buffer with input and open - drain output, tri - state notes: 1. endian value is latched only at the rising edge of nreset: when nreset is low, the endian (gp c3) pin operates in input mode; nreset becomes high, the endian pin will automatically switch to output mode. 2. iicsda, iicsclk, pci_nserr, and pci_ninta pins are of open - drain type. 3. ai/ao means analog input/output.
preliminary data she et S3C2800 microcon troller 7 table 2. 208 - pin lqfp pin assignment pin # pin name default function i/o state @initial i/o type 1 nsdcs2/ndras2/gpa4 nsdcs2 o/io phbsu50ct8sm 2 nsdcs3/ndras3/gpa5 nsdcs3 o/io 3 vdd3op vdd3op p vdd3op 4 vss3op vss3op p vss3op 5 ndcas0/gpa6 ndcas0 o/io phbsu50ct8sm 6 ndcas1/gpa 7 ndcas1 o/io 7 ndcas2/nsdcas/gpb0 nsdcas o/io 8 ndcas3/nsdras/gpb1 nsdras o/io 9 sdcke sdcke o phob8 10 sdclk sdclk o phob12 11 nbe0/nwbe0/dqm0/gpb2 dqm0 o/io phbsu50ct8sm 12 nbe1/nwbe1/dqm1/gpb3 dqm1 o/io 13 nbe2/nwbe2/dqm2/gpb4 dqm2 o/io 14 nbe3/nwbe3/dqm3/gpb5 dqm3 o/io 15 data16 data16 i/o phbsu50ct12sm 16 addr16 addr16 o phot8 17 data17 data17 i/o phbsu50ct12sm 18 addr17 addr17 o phot8 19 data18 data18 i/o phbsu50ct12sm 20 addr18 addr18 o phot8 21 vdd3op vdd3op p vdd3op 22 vss3op vss3op p vss3op 23 data19 data19 i/o phbsu50ct12sm 24 addr19 addr19 o phot8 25 data20 data20 i/o phbsu50ct12sm 26 addr20 addr20 o phot8 27 vdd vdd p vdd1ih 28 vss vss p vss3i 29 data21 data21 i/o phbsu50ct12sm 30 addr21 addr21 o phot8 31 data22 data22 i/o phbsu50ct12sm 32 addr22 addr22 o phot8 33 data23 data23 i/o phbsu50ct12sm 34 addr23 addr23 o phot8 35 data24 data24 i/o phbsu50ct12sm
S3C2800 microcontrol ler data sheet 8 table 2. 208 - pin lqfp pin assignment (continued) pin # pin name default function i/o state @initial i/o ty pe 36 addr24 addr24 o phot8 37 data25 data25 i/o phbsu50ct12sm 38 data26 data26 i/o 39 data27 data27 i/o 40 data28 data28 i/o 41 vdd3op vdd3op p vdd3op 42 vss3op vss3op p vss3op 43 data29 data29 i/o phbsu50ct12sm 44 data30 data30 i/o 45 data31 data31 i/o 46 noe noe o phob8sm 47 nwe nwe o 48 gpb6/nwait gpb6 io phbsu50ct8sm 49 gpb7/clkout gpb7 io 50 gpc0 gpc0 io 51 gpc1 gpc1 io 52 gpc2 gpc2 io 53 gpc3/endian endian i(1) 54 ntrst ntrst i phis 55 tck tck i phis 56 tms tms i phis 57 tdi tdi i phis 58 tdo tdo o phot8 59 irin irin i phis 60 gpd0/iicsda0 gpd0 io(2) phbsu50cd4sm 61 gpd1/iicsclk0 gpd1 io(2) 62 gpd2/iicsda1 gpd2 io(2) 63 gpd3/iicsclk1 gpd3 io(2) 64 gpd4/rxd0 gpd4 io phbsu50ct8sm 65 gpd5/txd0 gpd5 io 66 gpd6/ncts0 gpd6 io 67 gpd7/nrts0 gpd7 io 68 nreset_out nreset_out o phob8 69 gpe0/rxd1 gpe0 io phbsu50ct8sm 70 gpe1/txd1 gpe1 io
preliminary data she et S3C2800 microcon troller 9 table 2. 208 - pin lqfp pin assignment (continued) pin # pin name default function i/o state @initial i/o type 71 gpe2/ncts 1 gpe2 io phbsu50ct8sm 72 gpe3/nrts1 gpe3 io 73 vdd vdd p vdd1ih 74 vss vss p vss3i 75 gpe4/nxdreq0 gpe4 io phbsu50ct8sm 76 gpe5/nxdack0 gpe5 io 77 gpe6/nxdreq1 gpe6 io 78 gpe7/nxdack1 gpe7 io 79 gpf0/extint0 gpf0 io 80 gpf1/extint1 gpf1 io 81 gpf2/extint2 gpf2 io 82 gpf3/extint3 gpf3 io 83 gpf4/extint4 gpf4 io 84 gpf5/extint5 gpf5 io 85 gpf6/extint6 gpf6 io 86 gpf7/extint7 gpf7 io 87 vdd3op vdd3op p vdd3op 88 vss3op vss3op p vss3op 89 xtal0 xtal0 ai(3) phsoscm16 90 extal0 ext al0 ao(3) 91 test test i phis 92 nreset nreset i phisu 93 xtal1 xtal1 i phsosck17 94 extal1 extal1 o 95 om0 om0 i(1) phis 96 om1 om1 i(1) 97 avdd avdd p vdd1t_abb 98 pllcap pllcap ao(3) poar50_abb 99 avss avss p vss1t_abb/vbb1_abb 100 pci_nrst pci_nrst i ptipci 101 pci_clk pci_clk i 102 pci_ngnt1 pci_ngnt1 io ptbpci 103 pci_ngntx2 pci_ngntx2 o ptopci 104 pci_ngntx3 pci_ngntx3 o 105 pci_nreq1 pci_nreq1 io ptbpci
S3C2800 microcontrol ler data sheet 10 table 2. 208 - pin lqfp pin assignment (continued) pin # pin name default fun ction i/o state @initial i/o type 106 vss3op vss3op p vss3op_pci 107 pci_nreqx2 pci_nreqx2 i ptipci 108 pci_nreqx3 pci_nreqx3 i 109 pci_ad31 pci_ad31 i/o ptbpci 110 pci_ad30 pci_ad30 i/o 111 pci_ad29 pci_ad29 i/o 112 pci_ad28 pci_ad28 i/o 113 vdd3op vdd3op p vdd3op_pci 114 pci_ad27 pci_ad27 i/o ptbpci 115 pci_ad26 pci_ad26 i/o 116 pci_ad25 pci_ad25 i/o 117 pci_ad24 pci_ad24 i/o 118 vss3op vss3op p vss3op_pci 119 pci_c3/nbe3 pci_c3/nbe3 i/o ptbpci 120 pci_idsel pci_idsel i ptipci 121 p ci_ad23 pci_ad23 i/o ptbpci 122 pci_ad22 pci_ad22 i/o 123 vdd vdd p vdd1ih_pci 124 vss vss p vss3i_pci 125 pci_ad21 pci_ad21 i/o ptb_pci 126 pci_ad20 pci_ad20 i/o 127 pci_ad19 pci_ad19 i/o 128 pci_ad18 pci_ad18 i/o 129 pci_ad17 pci_ad17 i/o 130 pci_ad16 pci_ad16 i/o 131 vss3op vss3op p vss3op_pci 132 pci_c2/nbe2 pci_c2/nbe2 i/o ptbpci 133 pci_nframe pci_nframe i/o 134 pci_nirdy pci_nirdy i/o 135 vdd3op vdd3op p vdd3op_pci 136 pci_ntrdy pci_ntrdy i/o ptbpci 137 pci_ndevsel pci_ndevsel i/o 138 pci_nstop pci_nstop i/o 139 pci_nlock pci_nlock i ptipci 140 pci_nperr pci_nperr i/o ptbpci table 2. 208 - pin lqfp pin assignment (continued)
preliminary data she et S3C2800 microcon troller 11 pin # pin name default function i/o state @initial i/o type 141 pci_nserr pci_nserr i/o(2) ptbdpci 142 pci_par pci_par i/o ptbpci 143 pci_c1/nbe1 pci_c1/nbe1 i/o 144 pci_ad15 pci_ad15 i/o 145 vss3op vss3op p vss3op_pci 146 pci_ad14 pci_ad14 i/o ptbpci 147 pci_ad13 pci_ad13 i/o 148 pci_ad12 pci_ad12 i/o 149 pci_ad11 pci_ad11 i/o 150 pci_ad1 0 pci_ad10 i/o 151 pci_ad9 pci_ad9 i/o 152 pci_ad8 pci_ad8 i/o 153 vdd3op vdd3op p vdd3op_pci 154 pci_c0/nbe0 pci_c0/nbe0 i/o ptbpci 155 pci_ad7 pci_ad7 i/o 156 pci_ad6 pci_ad6 i/o 157 pci_ad5 pci_ad5 i/o 158 vss3op vss3op p vss3op_pci 159 pci_ad4 pci_ad4 i/o ptbpci 160 pci_ad3 pci_ad3 i/o 161 pci_ad2 pci_ad2 i/o 162 pci_ad1 pci_ad1 i/o 163 pci_ad0 pci_ad0 i/o 164 pci_ninta pci_ninta i/o(2) phbsud4 165 data0 data0 i/o phbsu50ct12sm 166 addr0 addr0 o phot8 167 data1 data1 i/o phbsu 50ct12sm 168 addr1 addr1 o phot8 169 data2 data2 i/o phbsu50ct12sm 170 addr2 addr2 o phot8 171 data3 data3 i/o phbsu50ct12sm 172 addr3 addr3 o phot8 173 vdd3op vdd3op p vdd3op 174 vss3op vss3op p vss3op 175 data4 data4 i/o phbsu50ct12sm
S3C2800 microcontrol ler data sheet 12 table 2. 208 - pin lqfp pin assignment (continued) pin # pin name default function i/o state @initial i/o type 176 addr4 addr4 o phot8 177 data5 data5 i/o phbsu50ct12sm 178 addr5 addr5 o phot8 179 data6 data6 i/o phbsu50ct12sm 180 addr6 addr6 o phot8 181 data7 data7 i/o phbsu50ct12sm 182 addr7 addr7 o phot8 183 data8 data8 i/o phbsu50ct12sm 184 addr8 addr8 o phot8 185 data9 data9 i/o phbsu50ct12sm 186 addr9 addr9 o phot8 187 vdd vdd p vdd1ih 188 vss vss p vss3i 189 data10 data10 i/o phbsu50ct12sm 190 addr10 addr10 o phot8 191 data11 data11 i/o phbsu50ct12sm 192 addr11 addr11 o phot8 193 vdd3op vdd3op p vdd3op 194 vss3op vss3op p vss3op 195 data12 data12 i/o phbsu50ct12sm 196 addr12 addr12 o phot8 197 data13 data13 i/o phbsu50ct12sm 198 addr13 add r13 o phot8 199 data14 data14 i/o phbsu50ct12sm 200 addr14 addr14 o phot8 201 data15 data15 i/o phbsu50ct12sm 202 addr15 addr15 o phot8 203 nscs0 nscs0 o phob8sm 204 nscs1/gpa0 nscs1 o/io phbsu50ct8sm 205 nscs2/gpa1 nscs2 o/io phbsu50ct8sm 206 nscs3/gpa2 nscs3 o/io phbsu50ct8sm 207 nsdcs0/ndras0 nsdcs0 o phob8sm 208 nsdcs1/ndras1/gpa3 nsdcs1 o/io phbsu50ct8sm
preliminary data she et S3C2800 microcon troller 13 signal descriptions table 3. S3C2800 signal descriptions signal i/o description bus controller om[1:0] i om [1:0] is used to determine s the bus width of static memory bank0 (boot rom). the pull - up/down resistor determines the logic level. 00 = 8 - bit 01 = 16 - bit 10 = 32 - bit 11 = not used addr[24:0] o addr [24:0] (address bus) outputs the memory address of the corresponding bank. data[31:0] io data [31:0] (data bus) inputs data during memory read and outputs data during memory write. the bus width is programmable among 8/16/32 - bit. nscs[3:0] o nscs[3:0] (static memory bank select) are activated when the address of a static memory is within the address region of each bank. the number of access cycles and the bank size can be programmed. nwe o nwe (write enable) indicates that the current bus cycle is a write cycle. nwbe[3:0] o write byte enable. nbe[3:0] o 16 - bit sram byte enable. nwait i request to prolong a current bus cycle. as long as nwait is low, the current bus cycle can?t be completed. noe o noe (output enable) indicates that the current bus cycle is a read cycle. endian i it determines whether or not the data t ype is l ittle - endian or b ig - endian. the pull - up/down resistor determines the logic level during the reset cycle. endian value is latched only at the rising edge of nreset: when nreset is low, the endian (gpc3) pin operates in input mode; nreset becomes high, the endian pin will automatically switch to output mode. 0 = l ittle - endian 1 = b ig - endian dram/sdram ndras[3:0] o row address strobe. ndcas[3:0] o column address s trobe. nsdras o sdram row address strobe. nsdcas o sdram column address strobe. nsdcs[3:0] o sdram chip select. dqm[3:0] o sdram data mask. sdclk o sdram clock (sdclk = hclk). sdcke o sdram clock enable. interrupt control unit extint[7:0] i external interrupt request. dma nxdreq[1:0] i external dma request. nxdack[1:0] o external dma acknowledge.
S3C2800 microcontrol ler data sheet 14 table 3. S3C2800 signal descriptions (continued) signal i/o description uart rxd[1:0] i uart receives data input. txd[1:0] o uart transmits data output. ncts[1:0] i uart clear to send input signal. nrts[1:0] o uart request to send output signal. iic - bus iicsda[1:0] io iic - bus data. iicscl[1:0] io iic - bus clock. remote control signal input interrupt irin i remote controller signal receive interrupt general - purpose i/o ports gpx[7:0] x 5 gpc[3:0] io general - purpose input/output ports (gpa[7:0], gpb[7:0], gpc[3:0], gpd[7:0] , gpe[7:0], gpf[7:0]) reset & clock nreset st nreset suspends any operation in progress and places S3C2800 into a known reset state. for a reset, nreset must be held to low level for a t least 4 cpuclk after the processor power is stabilized. nreset_out o the nreset_out pin is asserted during hardware reset(por,nreset), software reset and watchdog reset. xtal0 ai crystal input for internal osc circuit for system clock. if it isn't used, xtal0 has to be high level. extal0 ao crystal output for internal osc circuit for system clock. it is the inverted output of xtal0. if it isn't used, it has to be a floating pin. pllcap ai loop filter capacitor for system clocks pll. (1uf ) xtal1 ai 32 khz crystal input for rtc. extal1 ao 32 khz crystal output for rtc. it is the inverted output of xtal1. jtag test logic ntrst i ntrst(tap controller reset) resets the tap controller at start. if debugger is used, a 10k pull - up resistor has to be connected. if debugger(black ice) isn't used, ntrst pin has to be low level or low active pulse. tms i tms (tap controller mode select) controls the sequence of the tap controller's states. a 10k pull - up resistor has to be connected to tms pin. tck i tck ( tap controller clock) provides the clock input for the jtag logic. a 10k pull - up resistor has to be connected to tck pin. tdi i tdi (tap controller data input) is the serial input for test instructions and data. a 10k pull - up resistor has to be connected to tdi pin. tdo o tdo (tap controller data output) is the serial output for test instructions and data.
preliminary data she et S3C2800 microcon troller 15 table 3. S3C2800 signal descriptions (continued) signal i/o description power vdd p S3C2800 core logic v dd (1.8 v). vss p S3C2800 core logic v ss . avdd p S3C2800 analog logic (pll loop filter) v dd (1.8v). avss p S3C2800 analog logic (pll loop filter) v ss . vdd3op p S3C2800 gpio port v dd (3.3 v). vss3op p S3C2800 gpio port v ss . pci - bus pci_ad[31:0] i/o pci address/data bus. multiplexed address and data bus. pci_c[3:0]/ nbe[3:0] i/o pci c (bus command) or byte enables. pci_par i/o pci - parity. parity is even across pci_ad[31:0] and pci_c[3:0]/nbe[3:0]. pci_par is valid one cycle after either an address or data phase. the pci device that drives pci _ad[31:0] is responsible for driving pci_par on the next pci bus clock. pci_nframe i/o pci_nframe is driven by the current pci bus master to indicate beginning and duration of a pci access. pci_ntrdy i/o the target of the current pci transaction drives pci_ntrdy. assertion of pci_ntrdy indicates that the pci target is ready to transfer data. pci_nirdy i/o the current pci bus master drives pci_nirdy. assertion of pc_nirdy indicates that the pci initiator is ready to transfer data. pci_nstop i/o the ta rget of the current pci transaction may assert pci_nstop to indicate to the requesting pci master that it wants to end the current transaction. pci_ndevsel i/o the target of the current pci transaction drives pci_ndevsel. a pci target asserts pci_ndevsel when it decodes an address and command encoding, and claims the transaction. pci_idsel i pci_idsel is used during configuration cycles to select the pci slave interface for configuration. pci_nperr i/o pci_nperr is used for reporting data parity erro rs on pci transactions. pci_nperr is driven active by the device receiving pci_ad[31:0], pci_c[3:0]/nbe[3:0], and pci_parity, two pci clocks following the data in which bad parity is detected. pci_nserr i/o pci_nserr is used for reporting address parity errors or catastrophic failures detected by a pci target. pci_nlock pci_nlock indicates an atomic operation to a bridge that may require multiple transactions to complet. when pci_nlock is asserted, non - exclusive transactions may proceed to a bridge t hat is not currently locked. a grant to start a transaction on pci does not guarantee a control of pci_nlock. locked transactions may be initiated only by the host bridges. pci_nreq1 i/o when internal arbiter is used, pci_nreq1 is input mode. or when external arbiter is used, pci_nreq1 is output mode.
S3C2800 microcontrol ler data sheet 16 table 3. S3C2800 signal descriptions (continued) signal i/o description pci_nreqx[3:2] i pci_nreqx[3:2] input when internal arbiter is used. request indicates to the arbiter that this agent desires use of the bus. this is a point - to - point signal. every master has its own pci_nreqx, which must be tri - stated, while pci_nrst is asserted. pci_ngnt1 i/o when internal arbiter is used, pci_ngnt1 is output mode. or when external arbiter is used, pci_ngnt1 is input mode. pci_ngntx[3:2] o pci_ngntx[3:2] output when internal arbiter is used. grant indicates to the agent that access to the bus has been granted. this is a point - to - point signal. every master has its own pci_ngntx, which must be ignored while pc i - nrst is asserted. pci_clk i pci_clk is used as the asynchronous pci clock. pci_nrst o pci specific reset pci_ninta o pci interrupt.
preliminary data she et S3C2800 microcon troller 17 electrical data absolute maximum rat ings table 4. absolute maximum rating symbol parameter rating unit v dd 1.8v core dc supply voltage 2.4 v v ddp 3.3v i/o dc supply voltage 3.8 v v in dc input voltage 3.3 v input buffer 3.8 v v out dc output voltage 3.3 v output buffer 3.8 v i latch latch - up current 200 ma t stg storag e temperature ? 65 to 150 o c recommended operatin g conditions table 5. recommended operating conditions symbol parameters condition min type max unit v dd 1.8v core dc supply voltage commercial 1.7 1.8 1.95 v v ddp 3.3v i/o dc supply voltage commercial 3.0 3.3 3.6 v v in dc input voltage 3.3v input buffer 3.0 3.3 3.6 v v out dc output voltage 3.3v output buffer 3.0 3.3 3.6 v t opr operating temperature commercial 0 70 o c i dd normal operating current (fclk : hclk : pclk = 1: 1/2 : 1/4) ma 1.8v core supply current fclk = 200mhz, v dd = 1.95v ? 210 300 3.3v i/o supply current fclk = 200mhz, v ddp = 3.6v ? 75 110 i dd1 idle mode current (fclk : hclk : pclk = 1: 1/2 : 1/4) ma 1.8v core supply current fclk = 200mhz, v dd = 1.95v ? 75 110 3.3v i/o supply current fclk = 200mhz, v ddp = 3.6v ? 15 30 i dd2 slow mode current (fclk : hclk : pclk = 1: 1/2 : 1/2) ma 1.8v core supply current fclk = 6mhz, v dd = 1.95v ? 15 30 3.3v i/o supply current fclk = 6mhz, v ddp = 3.6v ? 5 10
S3C2800 microcontrol ler data sheet 18 dc electrical characteristics table 6. normal i/o pad dc electrical characteristics (v dd = 1.8 v - 0.1 v/+0.15 v, v ddp = 3.3 v 0.3 v, t opr = 0 to 70 c) symbol parameters condition min type max unit v ih high level input voltage v lvcmos interface 2.0 v il low level input voltage v lvcmos interface 0.8 vt switching threshold 1.4 v vt+ schmitt trigger, positive - going threshold cmos 2.0 v vt - schmitt trigger, negative - going threshold c mos 0.8 i ih high level input current m a input buffer v in = v ddp - 10 10 i il low level input current m a input buffer v in = v ss - 10 10 input buffer with pull - up - 120 - 66 - 20 v oh high level output voltage v type b4 i oh = - 4 ma 2.4 type b8 i oh = - 8 ma 2.4 type b12 i oh = - 12 ma 2.4 v ol low level output voltage v type b4 i ol = 4 ma 0.4 type b8 i ol = 8 ma 0.4 type b12 i ol = 12 ma 0.4 c in input capacitance any input and bi - directional buffers 4 pf c out output capacitance any output buffers 4 pf
preliminary data she et S3C2800 microcon troller 19 table 7. pci i/o pad dc electrical characteristics (v dd = 1.8 v - 0.1 v/+0.15 v, v ddp = 3.3 v 0.3 v, t opr = 0 to 70 c) symbol parameters condition min type max unit v ih high level input voltage 0.47v ddp v ddp +0.5 v v il low level input voltage - 0.5 0.33v ddp v i i input leakage current - 10 10 m a v oh high level output voltage i oh = - 500 m a 0.9v ddp v v ol low level output voltage i ol = 1500 m a 0.1v ddp v
S3C2800 microcontrol ler data sheet 20 mechanical data package dimensions 208-lqfp-2828 #208 28.00 0.20 30.00 0.30 28.00 0.20 30.00 0.30 0.10 max 0.127 + 0.10 - 0.05 0~8 note : dimensions are in millimeters. #1 0.50 ??0.20 0.10 0.05 1.40 0.10 1.60 max 0.50 (1.25) + 0.10 - 0.05 0.20 0.08 max figure 3. 208 - lqfp - 2828 package dimensions

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